ASIC RTL DESIGN ENGINEER, MACHINE LEARNING ACCELERATORS

Company: Google
Location: Madison
Posted on: October 28, 2024

Job Description:

Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.Experience in logic design, functional, and Power, Performance and Area (PPA) closure.Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.7 years of experience in ASIC design and in one or more successful ASIC products from concept to silicon.Experience applying engineering best practices (e.g., code review, testing, refactoring).Experience applying computer architecture principles to solve open-ended problems.Knowledge of computer networks and machine learning.Understanding of computer architecture/memory subsystem architecture. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate machine learning computation in Google's data centers. You will participate in the microarchitecture, design, documentation, and implementation of the next generation of machine learning center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Define micro-architecture specifications and take ownership of one or more modules and implement Register-Transfer Level (RTL).Create simple test benches and debug complex logic simulation.Converge functionality and Power, Performance and Area (PPA) of the design.Work closely with software teams to ensure solutions. Contribute to design methodology, libraries and code review.

Keywords: Google, Palatine , ASIC RTL DESIGN ENGINEER, MACHINE LEARNING ACCELERATORS, Engineering , Madison, Illinois